A Design Method of Address Generators Using Hash Memories

An address generator produces a unique address from 1 to k when the input that matches one of k registered vectors, and produces 0 for other inputs. This paper presents a method to design an address generator using a hash memory and an LUT cascade. The hash memory realizes about 90% of the registered vectors, while the LUT cascade realizes the remaining 10% of the registered vectors. This method uses a non-disjoint functional decomposition to reduce the size of memory. The experimental results using lists of English words show that the usefulness of the approach. The total amount of memory is only 20% to 25% of the memory necessary to implement the function by using an LUT cascade alone. Theoretical analysis supports the experimental results.